1. Field of the Invention
The present invention relates in general to a semiconductor device having the Silicon On Insulator (SOI) structure, and more particularly to a power IC monolithically integrating in it high blocking voltage power elements and control circuits and also to a hybrid IC or an intelligent power module in which high breakdown voltage power element chips and control-circuit chip are mounted on a prescribed substrate.
2. Description of the Prior Art
Recently, the developments of the power ICs have been activated. In the field of the insulation/isolation technology, the dielectric isolation (DI) technique has been developed in a multifarious manner as well as the brushing up of the direct wafer bonding technique and the SOI technique, while the dielectric insulation structure which fits larger power handling capability applications has been improved. In the field of the device design technology, on the other hand, constant advances have been made in the realization of higher-performance composite devices incorporating bipolar transistors and MOS transistors and also multi-functional devices including high-accuracy analog CMOS transistors. Also, even higher levels of intelligent devices in which various types of circuits are integrated have been further advancing, while the level-shift circuit technology has been actively developed to eliminate potential differences between the low-voltage control circuitry and the high-voltage output circuitry. Moreover, development examples of various types of power ICs utilizing all of those techniques have been reported, accelerating their practical applications.
In each of the power IC chips are merged many elements having different performances and structures desired. In their manufacturing, therefore, the technique of isolating those elements adjacent each other is fundamental. One of those inter-element isolation techniques is known as the DI technique shown in FIGS. 1A and 1B. The DI technique generally employs such a structure that the top surface of the SOI substrate is partially trenched by means of etching and, then, inside thus formed trenches are filled dielectrics 12. The DI technique decreases the inter-element parasitic effects at the same time as increasing the dielectric breakdown voltage, thus expecting future application as an inter-element isolation technique in an even wide variety of fields. FIG. 2 is a cross-sectional view of the power IC referred to as an intelligent power device in which a lateral power MOSFETs and control circuits, here CMOS control circuits, are monolithically integrated in an SOI substrate (wafer) structure. In the power IC shown in FIG. 2, a plurality of islands, each of them is called an active layer 13, are divided and isolated by using the DI technique and formed on an SOI oxide film 10. The p-type silicon substrate, which acts as a base substrate (supporting substrate) 11 in the SOI structure, is generally connected to the ground (GND potential) fixedly.
In such a structure as shown in FIG. 2, n-type active-layer islands 13 isolated from each other by dielectrics 12 are biased to various potential levels, one of which may produce inversion layer at the bottom of the active layers 13, i.e. at the boundary between an SOI oxide film 10 and the active layers 13, depending on the relationship between the base substrate 11 and the island 13, giving rise to some serious problems depending on the operational condition of the elements.
FIGS. 3A and 3B show the schematic diagram of two examples of such problems; the former indicates a case where an n-channel LDMOS transistor (Lateral Double-Diffused MOSFET) is turned on as a low-side switch and the latter, a case where an n-channel LDMOS is turned on as a high-side switch. In FIG. 3A, an n.sup.+ -type source region 21 of the LDMOS transistor is connected to the ground (GND potential), while in FIG. 3B, LDMOS's n.sup.+ -type drain region 23 is connected to the high-voltage power supply and, at the same time, n.sup.+ -type source region 21 is grounded via a load, so that the n-type active layer 13 is in the floating status. Here the load of the high-side switch may be an active element or circuitry such as the low-side switch.
In the case where, as shown in FIG. 3B, the LDMOS transistor is used as a high-side switch, the effective thickness X.sub.2 of the drift region formed in the n-type active layer 13 becomes thinner because an inversion layer 19 is formed, increasing the forward voltage drop (on-state voltage drop) V.sub.F. For the low-side switch, the effective thickness of the drift region is X.sub.1, almost the same as the thickness of the n-type active layer 13, whereas for the high-side switch, that effective thickness is X.sub.2, smaller than X.sub.1. This effect is remarkable especially where the n-type active layer 13 is thin.
FIGS. 4A through 4D show another example of the problem that an inversion layer 19 occurs at the boundary between an SOI oxide film 10 and an n-type active layer 13 in a power IC which comprises an Insulated Gate Bipolar Transistor (IGBT) or other output elements used as a high-side switch and a high-side CMOS control circuit which controls this output element. As shown in the cross-sectional view in FIG. 4A, the high-side CMOS control circuit consists of an n-MOS unit transistor having an n.sup.+ -type source region 21 and an n.sup.+ -type drain region 23 and a p-MOS unit transistor having a p.sup.+ -type source region 25 and a p.sup.+ -type drain region 24. The high-side CMOS control circuit, which controls an output device used as a high-side switch, would operate generally with the output device IGBT's emitter region (or power MOSFET's source region) and the n-MOS transistor's n.sup.+ -type source region 21 being connected to a common potential. Namely, the reference potential at the n-MOS transistor's n.sup.+ -type source region 21 of the CMOS transistor is a floating potential dictated by an operation condition. Because the potential of the n-type active layer 13 having the high-side CMOS control circuit becomes higher when the output device is ON, a p-type inversion layer 19 is generated at the bottom. Therefore, as shown in FIG. 4B, a parasitic pnp-type bipolar transistor occurs between the p-MOS transistor's p.sup.+ -type source region 25 and the p-type inversion layer 19, easily giving rise to a latchup phenomenon as compared to the case where that output device is OFF. Moreover, as shown in FIGS. 4C and 4D, when the active layer becomes even thinner, specifically 0.5 micrometer to 1.0 micrometer approximately, both the p-MOS transistor's p.sup.+ -type source region 25 and p.sup.+ -type drain region 24 reach an oxide layer 10 at the bottom, so that when the p-type inversion layer 19 is formed, a leakage current flows between the p.sup.+ -ype drain and source regions 24 and 25.
To solve such troubles, there are available the following:
(1) A method (first method) of changing the potential of the base substrate 11 by equalizing it to the potential of the source (or emitter) of an output device used as a high-side switch; and PA1 (2) another method (second method) of making the SOI structure's oxide film 10 very thick to decrease the parallel-plate MOS capacitance so that no inversion layer is formed easily.
Generally, however, the number of output devices used as high-side switches is not always limited to one and also each of them would operate independently. In contrast, the base substrate 11 would generally operate as the common region staying at a same potential in the structure, so that the first method is often impossible and, even if possible, it has a problem that the structure becomes complicated. The second method, on the other hand, is difficult in practice to carry out because it is necessary to make the oxide layer 10 thick enough to decrease the MOS capacitance considerably and, even if carried out, it suffers from expensive manufacturing costs.